Circuits for intrachip communications and networks-on-chip

Using full-rail interfaces on chip (in which CMOS inverters drive CMOS over RC-dominated interconnect) is a very energy inefficient means of communication (for a given amount of bandwidth density) and results in unnecessarily long wire latencies. We have been developing techniques to take full advantage of the transmission line properties of on-chip wires to achieve high-bandwidth, low-latency, and low-energy on-chip interconnects. One testchip, shown below, uses distributed shunt negative conductance elements to compensate for transmission line losses in a 14-mm long link.

Related Publications

A. P. Jose and K. L. Shepard, “Distributed loss-compensation techniques for energy-efficient low-latency on-chip communications” IEEE Journal of Solid-State Circuits, Vol. 42, June, 2007, pp. 1415-1424.

Abstract

In this paper, we describe the use of distributed loss compensation to provide nearly transmission-line behavior for long on-chip interconnects. Negative impedance converters (NICs) inserted at regular intervals along an on-chip line are shown to reduce losses from more than 1 dB/mm to less than 0.3 dB/mm at 10 GHz. Results are presented for a 14-mm 3-Gb/s on-chip double-data-rate (DDR) link in 0.18- m CMOS technology, with a measured latency of 12.1 ps/mm and an energy consumption of less than 2 pJ/b with a BER 10 14. This constitutes a factor-of-three improvement in power and a one-and-a-half-times improvement in latency over an optimally repeated RC line of the same wire width.

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A. P. Jose, G. Patounakis, and K. L. Shepard, “Pulse current-mode signalling for nearly speed-of-light intrachip communications” IEEE Journal of Solid-State Circuits, Vol. 41, April, 2006, pp. 772-780.

Abstract

In this paper, we describe the design of on-chip repeater-less interconnects with nearly speed-of-light latency. Sharp current-pulse data transmission is used to modulate transmitter energy to higher frequencies, where the effect of wire inductance is maximized, allowing the on-chip wires to function as transmission lines with considerably reduced dispersion. A prototype 8-Gb/s serial link employing this pulsed current-mode signaling in a 0.18- m CMOS process is described and measured.

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A. P. Jose and K. L. Shepard, “Distributed loss compensation for low-latency on-chip interconnects” Digest of Technical Papers, International Solid-State Circuits Conference, 2006.

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A. P. Jose, G. Patounakis, and K. L. Shepard, “Near speed-of-light on-chip interconnects using pulsed current-mode signalling” Symposium on VLSI Circuits, 2005.

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Measurement and modelling of variability in nanometer-scale CMOS

Process variability is a critical concern in nanometer-scale CMOS, owing to random device fluctuations (dopant fluctuation, line-edge roughness) and also reticle and proximity effects, which have difficult-to-predict impacts on device characteristics. Traditionally, process variability is characterized by one of two methods: either individual devices with pads are characterized on an automated wafer stepper or a ‘silicon dense’ structure of ring oscillators is used to find correlations between frequency and variation. The first method provides high accuracy at the cost of large area overhead and low information throughput. The second method, although providing higher throughput, ‘integrates’ all the characteristics of multiple devices into one measured number dramatically reducing information content

Recent methods focus on multiplexed transistor arrays because they provide high-density access to multiple devices for characterization. In our work, we have been designing on-chip current-voltage (I-V) measurement circuits that allow for rapid characterization of a large, dense array of multiplexed devices, using a four-point Kelvin-measurement approach to eliminate the effects of switch resistances and allowing for current measurements with nA resolution. Additionally, we have developed a novel, gate-leakage-insensitive on-chip charge-based capacitance measurement (CBCM) technique for capacitance-voltage (C-V)

characterization with aF resolution. Our CBCM technique enables us to characterize individual devices with circuit-representative dimensions in 45-nm CMOS, while at the same time largely reusing the on-chip measurement infrastructure already available for I-V characterization. More importantly, our combined C-V/I-V characterization approach allows us to not only study the variability in both sets of characteristics at the individual device level, but also to examine the correlation between them. As a result, by simultaneously observing and correlating the variability in the two measured sets of transistor characteristics, we are better able to infer the underlying physical causes of device variability.

Random telegraph noise (RTN) has been another source of growing concern in modern deep-sub-micron CMOS technologies. RTN is caused by the trapping and de-trapping of individual charges near the MOS transistor channel-oxide interface, resulting in telegraph-like modulation of the transistor current, and is expected to increase in magnitude with reduction of device size, eventually overtaking other traditional sources of device variability, such as random dopant fluctuations. RTNOur on-chip I-V characterization approach is ideally suited for RTN characterization, as it allows relatively high-frequency (up to 100 KHz) current measurements with nA resolution on large statistical device sets. In our work, we have measured RTN noise in a low-power 45-nm process, and we have developed a characterization and statistical modeling methodology that allows us to capture the effects of RTN on transistor performance.

Related Publications

S. Realov and K. L. Shepard, “On-Chip Combined C-V/I-V Transistor Characterization System in 45-nm CMOS,” Symposium on VLSI Circuits, 2011.

Abstract

An on-chip transistor characterization system for combined C-V/I-V characterization is presented. Capacitance measurement uses a quasi-static charged-based measurement technique with atto-Farad resolution. Random and systematic variability in device I-V and C-V characteristics is studied. The random variability in intrinsic gate capacitance is shown to exhibit Pelgrom scaling. Correlation between I-V and C-V measurements is used to identify systematic channel-length variation gradients in a device array.

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S. Realov and K. L. Shepard, “Random telegraph noise in 45-nm CMOS: analysis using an on-chip test and measurement system,” International Electron Devices Meeting, 2010, pp. 28.2.1-28.2.4.

Abstract

RTN measurements in 45-nm CMOS across device bias and geometry using an on-chip characterization system are reported. An automated methodology for extracting RTN levels, amplitude and dwell times is developed. Complex RTN magnitude is statistically modeled, and device size and bias parameter dependencies of the developed model are examined.

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V. Wang and K. L. Shepard, “On-chip transistor characterisation arrays for variability analysis” Electronics Letters, Vol. 43, No. 15, July, 19, 2007.

Abstract

efficiently and accurately characterise large, dense arrays of transistors for variability studies is designed. The prototype macro is used to perform current–voltage characterisation of a 2.8 mm2, 1600- transistor array with digital interfaces.

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CMOS fluorescence-based active microarrays

This project is a multidisciplinary effort to novelly exploit CMOS silicon microelectronics in the design of low-cost, portable, self-contained “gene chip” technology for nucleic acid measurement and detection. Much of this effort is focussed on developing active substrates based on fluorescence detection. One such active microarray is shown below, capable of time-resolved fluorescence detection for background rejection (though time-gating) and fluorescence-lifetime measurement. DNA probe is attached directly to the chip surface for detection.

Related Publications

T.-C. Huang, S. Sorgenfrei, K. L. Shepard, P. Gong, and R. Levicky, “A CMOS array sensor for sub-800-ps time-resolved fluorescence detection” IEEE Custom Integrated Circuits Conference, 2007.

Abstract

This paper describes the design of an active CMOS sensor array for fluorescence applications which enables timegated, time-resolved fluorescence spectroscopy. The 64 x 64 array is sensitive to photon densities as low as 8 x 106 photons/ cm2 with 64-point averaging and, through a differential pixel design, has a measured impulse response of better than 800 ps. Applications include both active microarrays and high-frame-rate imagers for fluorescence lifetime imaging microscopy.

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D. E. Schwartz, E. Charbon, and K. L. Shepard, “A single-photon avalanche diode imager for fluorescence lifetime applications” Symposium on VLSI Circuits, 2007, pp. 144-245.

Abstract

A 64-by-64-pixel CMOS single-photon avalanche diode (SPAD) imager for time-resolved fluorescence detection features actively quenched and reset pixels, allowing gated detection to eliminate pile-up nonlinearities common to most time-correlated single-photon counting (TCSPC) approaches. Reset Timing information is collected using an on-chip time-tocalb calibrated digital converter (TDC) based on a counter and a supply- interpolators regulated delay-locked loop (DLL).

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G. Patounakis, K. L. Shepard, and R. Levicky, “Active CMOS array sensor for time-resolved fluorescence detection” IEEE Journal of Solid-State Circuits, November, 2006

Abstract

Surface-based sensing assays based on fluorescence-based detection have become commonplace for both environmental and biomedical diagnostics. Traditional array scanners are expensive, large, and complex instruments. This paper describes the design of an active CMOS biosensor substrate for fluorescence-based assays that enables time-gated, time-resolved fluorescence spectroscopy without the need for an external reader. The array is sensitive to photon densities as low as 1 15 108 cm2, has a dynamic range of over 74 dB, and has subnanosecond timing resolution. Sensitivity is achieved through subsampling and averaging.

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G. Patounakis, K. L. Shepard, and R. Levicky, “Active CMOS biochip for time-resolved fluorescence detection” Symposium on VLSI Circuits, 2005.

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Fluorescence Lifetime Imagers

Traditional Fluorescence Lifetime Imaging Microscopy systems use laser scanning techniques in concert with a single photon detector, such as a photomultiplier tube or avalanche photodiode, to construct lifetime based images using Time Correlated Single Photon Counting (TCSPC).  In order to acquire enough data within each pixel to determine the lifetime, thousands of samples must be taken.  As a result, the time required to capture a single frame can be several to tens of seconds, which presents a limit to the types of biological processes that can be monitored using FLIM.  The focus of this project is creating a CMOS-based Single Photon Avalanche Diode (SPAD) array that is capable of acquiring multiple frames per second, which would make real-time FLIM imaging of biological processes possible.

Our most recent array design was capable of a maximum frame rate of 3.9 Hz and consisted of a 64 x 64 SPAD array with integrated timing and pixel control circuitry in 0.35μm technology. The image on this page below shows a FLIM image of quantum dots (in color) next to a CCD image showing the location of the quantum dots on the array.

 

Our recent efforts are focused on developing a SPAD array in a standard CMOS process flow for a more advanced technology node. We have developed a low-noise SPAD in 0.13μm technology that will enable higher imaging rates through improved circuit performance. A full imaging array based on this SPAD design is currently under development.

Related Publications:

R. M. Field, J. Lary, J. Cohn, L. Paninski, and K. L. Shepard, “A low-noise, single-photon avalanche diode in standard 0.13 μm complementary metal-oxide-semiconductor process,” Applied Physcis Letters, 97, 211111 (2010).

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Abstract

We present the design and characterization of a single-photon avalanche diode SPAD fabricated with a standard 0.13 m complementary metal-oxide-semiconductor process. We have developed a figure of merit for SPADs when these detectors are employed in high frame-rate fluorescent lifetime imaging microscopy, which allows us to specify an optimal bias point for the diode and compare our diode with other published devices. At its optimum bias point at room temperature, our SPAD achieves a photon detection probability of 29% while exhibiting a dark count rate of only 231 Hz and an impulse response of 198 ps.

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D. E. Schwartz, E. Charbon, and K. L. Shepard, “A single-photon avalanche diode imager for fluorescence lifetime applications” Symposium on VLSI Circuits, 2007, pp. 144-245.

Abstract

A 64-by-64-pixel CMOS single-photon avalanche diode (SPAD) imager for time-resolved fluorescence detection features actively quenched and reset pixels, allowing gated detection to eliminate pile-up nonlinearities common to most time-correlated single-photon counting (TCSPC) approaches. Reset Timing information is collected using an on-chip time-tocalb calibrated digital converter (TDC) based on a counter and a supply- interpolators regulated delay-locked loop (DLL).

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Piezoelectrics-on-CMOS

Traditional chemical and biological assays rely on secondary reporters for detection of binding events, as with the use of fluorescent reporters for microarrays or colorimetric enzyme labels for immunoassays. These techniques have been very effective, but they add cost and complexity to assays, provide only end-point interrogation, and often limit multiplexed detection. A move towards real-time, label free assays provides many advantages. We are working towards this goal using piezoelectric resonant sensors on CMOS.

A thin-film bulk acoustic resonator (FBAR) can be employed as the micron-scale equivalent of a quartz crystal microbalance (QCM); mass attaches to the surface of a piezoelectric crystal, causing the resonance frequency to decrease slightly. Whereas a quartz crystal sensor operates in the megahertz regime, FBAR structures resonate in the low gigahertz regime. Their small size allows array integration of sensors, similar to a microarray, and the increased frequency allows increased sensitivity. Both of these features make FBARs ideal for direct CMOS integration, where sensors can be built in dense arrays and used without bulky external measurement equipment.

In this research, we have fabricated FBAR structures monolithically on a custom CMOS substrate. The resonators are solidly mounted, and mechanical isolation is achieved with a multi-layer acoustic reflector. Monolithic fabrication enables an array of integrated resonators, and the underlying CMOS circuitry forms an independent FBAR-CMOS oscillator around each device. The CMOS substrate also contains a dedicated digital frequency counter for each oscillator, enabling parallel on-chip

frequency measurement of all sites. image 3On-chiposcillators at 850 MHz and 1.45 GHz have been demonstrated, and the integrated sensors have a mass sensitivity many times higher than that of a traditional QCM. In addition to sensing, this methodology may find significant utility in RF applications, where it enables monolithic integration of high-Q elements directly on a standard CMOS substrate.

The sensor platform has been applied to volatile organic compound (VOC) quantification, where a semi-selective polymer layer absorbs low concentrations of VOC vapors, causing a frequency shift in the underlying resonator. This interaction is reversible, allowing vapor concentration to be quantified continuously and in real time. Future work will extend this technology to broader chemical and biological sensing applications.

Related Publications:

M. L. Johnston, H. Edrees, I. Kymissis, and K. L. Shepard, “Integrated VOC Vapor Sensing on FBAR-CMOS Array,” The 25th IEEE International Conference on Micro Electro Mechanical Systems (MEMS 2012), pp. 846-849, 2012.

Abstract

This paper reports first results of volatile organic compound (VOC) detection on a monolithically integrated film bulk acoustic resonator (FBAR) array on a silicon integrated circuit substrate. The combined sensor platform uses thin polymer layers as gas absorbers for individual FBAR functionalization, and frequency shifts are measured on-chip in response to changing VOC concentration. Integrating sensors, drive, and read- out functionality on a single CMOS die enables a robust, multiplex sensor platform and obviates external measurement equipment.

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Johnston, M. L.; Kymissis, I.; Shepard, K. L., “FBAR-CMOS Oscillator Array for Mass-Sensing Applications,” Sensors Journal, IEEE , vol.10, no.6, pp.1042-1047, June 2010.

Abstract

Thin-film bulk acoustic resonators (FBAR) are an effective platform for sensitive biological and chemical detection, where their high operating frequencies make them many times more sensitive than a quartz crystal microbalance. Here, we present a monolithic, solidly mounted FBAR oscillator array on CMOS for mass-sensing applications. Through monolithic integration with CMOS drive circuitry, we aim to overcome the spatial and parasitic load limitations of externally coupled resonators to build dense sensor arrays without specialized fabrication techniques. The sensors in this work are constructed in a 6 4 array atop a 0.18μm CMOS active substrate, and mass sensitivity comparable to off-chip FBAR sensors is demonstrated.

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M.L. Johnston, I. Kymissis, and K.L. Shepard, “An array of monolithic FBAR-CMOS oscillators for mass-Sensing applications,” Proc. of 15th International Conference on Solid-State Sensors, Actuators & Microsystems (Transducers ’09), June 2009.

Abstract

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